The present invention relates in general to processing semiconductor devices and, more particularly, to etching composite copper layers on semiconductor devices.
Historically, passive components such as capacitors and inductors required for tuning, LC tanks, AC coupling, impedance matching and filtering requirements were mounted external to semiconductor devices containing active components. External mounting creates problems that a module designer must take into account when perfecting the design. These problems may include parasitics associated with the interface between the active and external passive devices, higher costs associated with additional space requirements and higher part count. In addition reliability may be compromised due to the higher part count and added connections that external mounting requires. Despite these drawbacks, external mounting has been the industry's practice due to the inability to effectively integrate passive components with active semiconductor devices.
One of the major problems has been the inability to form the patterned structures required, in a manner consistent with semiconductor processing techniques, with sufficient accuracy. Attempts at integrating inductors, for example, have consisted of deposited aluminum or gold films to maximum thicknesses off approximately 3 microns. These films are then etched to produce the desired structures. However, the wet etch techniques employed have resulted in less than desirable results, caused by high etch rates, non-uniformity and under cutting. Dry etch techniques, used extensively to accurately etch aluminum films 1 micron or less thick, are too slow and/or costly for etching films greater than 1 micron. These aluminum or gold inductors also suffer from high series resistance due to their thin structure and relatively high resistivity as compared to copper.
Hence, to take advantage of copper's low relative resistivity and low cost with respect to other metals such as gold, a need exists for a method of forming thick copper layers with accurately dimensioned patterns on semiconductor devices.